As shown in FIG. 5, an array board 1 to be used as the liquid panel is provided with a plurality of gate lines G arrayed in rows, a plurality of signal lines D arrayed in columns, and a plurality of pixels PI each of which is arranged at the intersections of the gate lines G with the signal lines D. The pixels PI include switching transistors (thin film transistors) Tr, retention capacitors C, and pixel electrodes (not illustrated).
If the switching transistors Tr are turned on, a writing electric potential VD from the signal lines D is inputted in the pixel electrode and the one end of the retention capacitor C. A common electric potential Vcom is inputted in the opposed electrode (not illustrated) arranged opposite to the pixel electrode and at the other end of the retention capacitors C so as to drive a liquid crystal element (not illustrated) located between the pixel electrode and the opposed electrode due to a difference in the electric potential of the pixel electrode and the opposed electrode. The retention capacitors C retain an electric potential that is applied between the pixel electrode and the opposed electrode for a predetermined period of time.
In the array step of manufacturing such an array board 1, with or without of a failure such as a pixel failure and a disconnection failure of the gate line G is inspected. These inspections are carried out by an inspection equipment 100 shown in FIG. 5. The inspection equipment 100 is provided with a gate driving circuit 101 for turning on the switching transistors Tr by applying a driving electric potential VGH to the one end of the gate line G, a writing circuit 102 for applying the writing electric potential VD in the signal line D, a reading circuit 103 for reading the electric charge quantity stored in the retention capacitor C, and a switching element 104 for connecting the signal line D to the writing circuit 102 or the reading circuit 103.
The inspection equipment 100 writes the electric charge in the retention capacitor C (the writing operation), and by reading the written electric charge (the reading operation), the inspection equipment 100 inspects to see if there is a failure. According to the writing operation, the gate line G applies the driving electric potential VGH to the selected gate line G and turns on the switching transistor Tr connected to the selected gate line G during a period of time of writing. In addition, the writing circuit 102 is connected to the signal line D that is selected by the switching element 104 and the writing circuit 102 applies the writing electric potential VD to the signal line D. Thereby, the electric charge is stored in the retention capacitor C within the pixel PI arranged at the intersection of the selected gate line G with the selected signal line D. After the writing operation, the gate driving circuit 101 stops applying of the driving electric potential VGH and the writing circuit 102 stops applying of the writing electric potential VD. Subsequently, the inspection equipment 100 starts the reading operation.
According to the reading operation, the gate driving circuit 101 turns on the switching transistor Tr again. In this time, the reading circuit 103 is connected to the selected signal line D through the switching element 104 and reads out the electric charge stored in the retention capacitor C upon the writing operation. On the basis of the read electric charge quantity, it is determined if a failure has occurred.
The pixel failure is determined based on whether or not the read electric charge quantity is equal to the electric charge quantity on a normal case that was measured in advance. On the other hand, the disconnection failure of the gate line G is determined based on whether or not the read electric charge quantity is 0. When the gate line G10 shown in FIG. 5 is disconnected at a point P10 between the gate driving circuit 101 and the switching transistor Tr10, even if the gate driving circuit 101 applies the driving electric potential VGH to the gate line G10, the electric potential VGH is not applied to the gate of the switching transistor Tr10. Therefore, even during the writing operation, the switching transistor Tr10 is not turned on, and the electric charge is not stored in a retention capacitor C10. In this case, it is determined that the gate line G10 is disconnected because the electric charge quantity that is read by the reading operation becomes 0.
In the meantime, in recent years, the liquid crystal panel has been made in a large size (e.g., one over 35 inches has been manufactured). The liquid crystal panel over 35 inches is applied with the driving electric potential VGH from the both sides of the gate line so as to drive the liquid crystal element. Since the gate line of the liquid crystal panel of a large size is longer than the conventional one, a resistance and a parasitic capacitance of the gate line are large. Therefore, if the driving electric potential is applied to the liquid crystal panel only from the one end of the gate line, a time that the electric potential gradually rises up to the driving electric potential from the one end to which the driving electric potential is applied to the other end thereof. In order to such a delay of the signal, the driving electric potentials are applied from the both ends of the gate line.
If the driving electric potentials are applied from the both ends of the gate line in a finished liquid crystal panel, even in the inspection of the pixel failure in the array step, it is necessary to apply the driving electric potentials from the both ends of the gate line. In the case of effecting an image inspection of the array board 1 of the large size by using the inspection equipment 100, the driving electric potential is applied only from the one end of the gate line G. In this case, the electric charge quantity to be stored in the retention capacitor upon the writing operation is decreased as the retention capacitor is located farther from the gate driving circuit 101 due to delay of the signal.
Therefore, even if the pixel is normal, the electric charge quantity stored in a time of period of writing is decreased, and there is a possibility that this normal pixel is determined as the pixel failure. If the writing time is made longer than the conventional case, this problem is solved, however, in this case, a property failure of the switching transistor Tr may not be detected. At last, it is necessary to effect the inspection of the pixel failure by applying the driving electric potentials from the both ends of the gate line.
However, if the driving electric potentials are applied from the both ends of the gate line, it is not possible to detect the disconnection failure of the gate line. This is because, if applying the driving electric potential VGH from the opposite ends of the gate line G10 in FIG. 5, even if the gate line is disconnected at the point P10, all switching transistors Tr connected to the gate line G10 are turned on and the electric charge in stored in each retention capacitor C.
In the image inspection, a method of applying the driving electric potentials to the both ends of the gate line is also available, and in the inspection of the disconnection failure of the gate line, a method of applying the driving electric potential only to the one end of the gate line is also available. However, in this case, a probe that is connected to the one end of the gate line should be detached upon the inspection of the disconnection failure, so that workload is increased. In addition, it is also available to inspect the disconnection failure by applying the driving electric potential from the one probe without detaching the probe, connecting an electric current detecting circuit to the other probe, and measuring the electric current flowing through the gate line. However, in this case, a switching circuit for switching the connection of the probe from the gate driving circuit into the electric current detecting circuit is required. There are about 1,000 pieces of the gate lines G on the array board 1, therefore, it is difficult to mount the switching circuit to accommodate all of these gate lines.